J. Cong, M. Ghodrat, M. Gill, B. Grigorian, H. Huang, and G. Reinman,
“Composable accelerator-rich microprocessor enhanced for adaptivity
and longevity,” in 2013 IEEE International Symposium on Low Power
Electronics and Design (ISLPED), Sep. 2013, pp. 305–310.
 B. Reagen, R. Adolf, Y. Shao, G.-Y. Wei, and D. Brooks, “MachSuite:
Benchmarks for accelerator design and customized architectures,” in
2014 IEEE International Symposium on Workload Characterization
(IISWC), Oct. 2014, pp. 110–119.
 J. Benson, R. Cofell, C. Frericks, C.-H. Ho, V. Govindaraju, T. Nowatzki,
and K. Sankaralingam, “Design, integration and implementation of the
DySER hardware accelerator into OpenSPARC,” in 2012 IEEE 18th
International Symposium on High Performance Computer Architecture
(HPCA), Feb. 2012, pp. 1–12.